Tesla Unveils SI Chip Roadmap: SI6 Promises 80x the Compute of AI4, Dojo 3 Returns
Key takeaway: Tesla has renamed its AI accelerator line from AI to SI — short for “super intelligence” — and laid out a roadmap in which the SI6 inference chip delivers 80 times the compute of today’s HW4, while the cancelled Dojo training program returns as a chiplet-based Dojo 3 (D3) aimed at space, training, and scaling.
What Tesla announced
Tesla has disclosed a revamped accelerator roadmap and rebranded its chip line under a “super intelligence” push, according to reporting on Tom’s Hardware’s coverage. The AI4, AI5 and AI6 generations become SI4, SI5 and SI6. The renaming is not cosmetic only: it follows Elon Musk’s confirmation that SpaceXAI would also become SpaceXSI, and Tesla’s own vehicle owner’s manuals had already started replacing “FSD Computer” with “SI Computer” in late October.
The headline number is SI6. Per Tesla, the sixth-generation inference chip will deliver 80 times the compute performance of the current fourth-generation HW4, with nine times its memory. It is expected to carry 144GB of memory, use a 2nm-class process at Samsung Foundry, and keep a multi-chip-module design. Tesla has a deal with Samsung Foundry to manufacture its sixth-generation inference accelerators through 2033, and SI6 is due in 2029–2030.
SI5 comes first. Tesla expects a 40-fold performance improvement over HW4 from SI5, which is expected to use a multi-chip-module design, be manufactured on a 3nm-class process at TSMC and a 2nm-class process at Samsung Foundry, and carry 96GB of memory with power consumption of 250W to 800W depending on the application. Musk attributed the expected gain to an eightfold increase in compute capability and a fivefold gain from silicon optimization.
Tesla SI chips compared
| Chip | Compute vs HW4 | Memory | Process | Status |
|---|---|---|---|---|
| HW4 (now SI4) | Baseline (est. 216–576 TOPS) | Believed 16GB GDDR6 | 7nm-class, Samsung | In Tesla vehicles today |
| SI5 | 40x | 96GB | 3nm TSMC / 2nm Samsung | In development; trial production reported |
| SI6 | 80x | 144GB | 2nm-class, Samsung | Due 2029–2030 |
One caution on the numbers: Tesla does not officially disclose absolute compute performance, memory capacity or power consumption for its chips. The TOPS figures are Tom’s Hardware estimates, derived from Musk’s earlier statement that HW4 is 3–8 times more powerful than HW3, which was rated at 72 TOPS. On that basis, SI5 would land at an estimated 8,640–23,040 TOPS and SI6 at 17,280–46,080 TOPS — but the publication itself cautions these are estimates, and SI6’s supported data formats are unknown.
Dojo 3 returns — as a chiplet design
The roadmap also brings back Tesla’s in-house Dojo training accelerator. Musk cancelled the wafer-scale Dojo project in August 2025 and disbanded the team; in January 2026 he said the program would return, with the third-generation chip aimed at space-based AI compute. Now Tesla describes D3 as a chiplet-based design combining 2.5D and 3D packaging with stacked high-bandwidth memory (HBM), a sharp break from the SRAM-centric architecture of the original Dojo D1.
Tesla has not disclosed D3’s compute performance, memory capacity, manufacturing process or development schedule, but says the accelerator is being optimized for “space, training, and scaling.” The reporting notes that extraterrestrial deployment could mean radiation hardening for at least some versions of the chip. It is also unclear whether Tesla has abandoned wafer-scale integration altogether.
The D3 pivot matters because it aligns Tesla’s training hardware with the direction the rest of the accelerator industry has converged on: chiplets plus HBM, where memory bandwidth next to the math is often the real constraint. For context, Tesla’s roadmap has been moving fast all year — Musk has talked about a nine-month chip design cycle, well under the 12-month cadence Nvidia and AMD work to, and has said AI5’s design is nearly complete with AI6 in early stages.
Why this matters
For Tesla owners, the roadmap is a promise about what future cars and robots can do. SI5 is the chip expected to push Tesla’s driver-assistance software toward near-perfect autonomy and substantially improve the Optimus humanoid robot’s reasoning, while SI6 is aimed at Optimus and data centers. For the wider AI industry, Tesla is now openly competing as a chipmaker: a vertically integrated stack — silicon, software, vehicles, robots, and potentially orbital compute — built on Samsung and TSMC foundry capacity rather than bought from Nvidia.
That ambition is also the risk. The 80x figure is a target for silicon due in 2029–2030, not a benchmarked product, and Tesla’s own history here includes a cancelled Dojo program and a pivot from wafer-scale designs. The roadmap gives the industry named milestones to track; the proof will be the silicon that actually ships. Readers watching the same space should also note Google’s Astra edge AI chip and Microsoft’s Maia 300 — custom silicon is now a strategic asset for every major AI player, not just the GPU makers.
Analysis: branding is part of the roadmap
Analysis: Renaming AI to SI is a deliberate reframing. “AI” describes what the chips do today — driver assistance. “Super intelligence” describes where Musk wants the program to end up: general-purpose compute for cars, robots, data centers, and orbit. The name change, the SI4/SI5/SI6 ladder, and the Dojo 3 revival all point the same way: Tesla wants its silicon read as infrastructure, not as a car part. That is a credible strategy given the foundry deals and the chiplet pivot — but it also raises the stakes. Every generation now carries an explicit performance multiple against HW4, and those multiples will be checked against shipping hardware.
Knowns, unknowns, and what to watch
Known: the SI naming, the SI5 40x and SI6 80x targets, the 144GB and 2nm details for SI6, the Samsung manufacturing deal through 2033, and the D3 chiplet-plus-HBM architecture.
Unknown: SI6’s supported data formats, D3’s performance, memory, process and schedule, whether wafer-scale integration is truly dead, and when SI5 reaches volume production.
What to watch: SI5 engineering samples and production timing, any Tesla disclosure of D3 specifications, and whether the nine-month design cadence Musk has described actually holds through 2027.
Frequently asked questions
What is Tesla’s SI chip lineup?
Tesla renamed its AI accelerators with the “SI” (super intelligence) label: AI4, AI5 and AI6 are now SI4, SI5 and SI6. SI4 is the current in-vehicle chip, SI5 is the next generation in development, and SI6 is the sixth-generation inference chip due in 2029–2030.
How much faster is SI6 than AI4?
Tesla says SI6 will deliver 80 times the compute performance of HW4 (AI4) and nine times its memory, with 144GB of memory on a 2nm-class Samsung process. Tom’s Hardware estimates that would amount to 17,280–46,080 TOPS, but cautions these are estimates because Tesla does not disclose absolute performance figures.
When will Tesla’s SI6 chip arrive?
SI6 is due in 2029–2030, according to the roadmap Tesla disclosed. Tesla has a deal with Samsung Foundry to manufacture its sixth-generation inference accelerators through 2033.
What is Dojo 3 (D3)?
Dojo 3 (D3) is Tesla’s revived in-house AI training accelerator. It uses a chiplet-based design with 2.5D and 3D packaging and stacked high-bandwidth memory, replacing the SRAM-centric architecture of the original Dojo D1. Tesla says it is optimized for “space, training, and scaling,” but has not disclosed its performance, memory, process or schedule.
Will SI chips power Tesla cars and Optimus?
Yes, in Tesla’s plan. SI5 is aimed at vehicles and the Optimus humanoid robot, while SI6 is intended for Optimus and data centers. SI4 (the renamed HW4) already powers Tesla vehicles today.
Sources: Mezha — Tesla outlines AI chip roadmap and rebrands accelerators as SI (Nov 6, 2026); DEV Community — Tesla unveils SI accelerator roadmap (Nov 6, 2026, summarizing Tom’s Hardware); Data Center Dynamics — Musk on the nine-month chip cycle and Dojo’s return.
